FrameBufferIP Handbook
Last modified by Paweł Eichler on 2021/03/08 13:38
Description
FrameBuffer controller with built-in configurable buffer.
Block Diagram
Register Map
ID 0x0 RO
FrameBuffer ID register
[31: 0] ID Always returns 0xdead2137
FrameBuffer ID register
[31: 0] ID Always returns 0xdead2137
ENABLE 0x04 RW
FrameBuffer enable register - controls functionalities of the IP
[31: 2] RSVD_0
[ 1: 1] REFRESH Enables fetching from external memory
[ 0: 0] ENABLE Global controller enable bit
FrameBuffer enable register - controls functionalities of the IP
[31: 2] RSVD_0
[ 1: 1] REFRESH Enables fetching from external memory
[ 0: 0] ENABLE Global controller enable bit
MODE 0x08 RW
Mode control register
[31:24] SOLID_BLUE
[23:16] SOLID_GREEN
[15: 8] SOLID_RED
[ 7: 2] RSVD_0
[ 1: 0] MODE 0-BUFFER, 1-TEST_PATTERN, 2-SOLID, 3-WHITE
Mode control register
[31:24] SOLID_BLUE
[23:16] SOLID_GREEN
[15: 8] SOLID_RED
[ 7: 2] RSVD_0
[ 1: 0] MODE 0-BUFFER, 1-TEST_PATTERN, 2-SOLID, 3-WHITE
WRAP 0x0C RW
Buffer wrap control register. Possible use case - tiled background
[31:16] Y_WRAP
[15: 0] X_WRAP
Buffer wrap control register. Possible use case - tiled background
[31:16] Y_WRAP
[15: 0] X_WRAP
ADDR_LO 0x10 RW
LSb of external memory
[31: 0] ADDR_LO
LSb of external memory
[31: 0] ADDR_LO
ADDR_HI 0x14 RW
MSb of external memory
[31: 0] ADDR_HI
MSb of external memory
[31: 0] ADDR_HI
RSVD 0x18 RW
Reserved
[31: 0] RSVD
Reserved
[31: 0] RSVD
RSVD 0x1C RW
Reserved
[31: 0] RSVD
Reserved
[31: 0] RSVD
SYNC_PIXELS 0x20 RW
SYNC pixels
[31:16] VSYNC Vertical SYNC pixels
[16: 0] HSYNC Horizontal SYNC pixels
SYNC pixels
[31:16] VSYNC Vertical SYNC pixels
[16: 0] HSYNC Horizontal SYNC pixels
BACK_PORCH 0x20 RW
Back porch pixels
[31:16] VBACK Vertical back porch pixels
[16: 0] HBACK Horizontal back porch pixels
Back porch pixels
[31:16] VBACK Vertical back porch pixels
[16: 0] HBACK Horizontal back porch pixels
ACTIVE_PIXELS 0x28 RW
Active pixels
[31:16] VACTIVE Vertical Active pixels
[16: 0] HACTIVE Horizontal Active pixels
Active pixels
[31:16] VACTIVE Vertical Active pixels
[16: 0] HACTIVE Horizontal Active pixels
FRONT_PORCH 0x2c RW
Front porch pixels
[31:16] VFRONT Vertical front porch pixels
[16: 0] HFRONT Horizontal front porch pixels
Front porch pixels
[31:16] VFRONT Vertical front porch pixels
[16: 0] HFRONT Horizontal front porch pixels
POLARITY 0x30 RW
Active pixels
[31:17] RSVD
[16] VPOL Vertical polarity
[15: 1] RSVD
[0] HPOL Horizontal polarity
Active pixels
[31:17] RSVD
[16] VPOL Vertical polarity
[15: 1] RSVD
[0] HPOL Horizontal polarity
Examples
Tiled background via GDB
Connect GDB to remote target (see GDB over JTAG) of RCHD-PF and execute following commands:
- restore to fill memory buffer in the FrameBuffer with static data that you want to display in RGB565 format (in this example it is 256x64 bitmap)
- enable displaying the memory content
- adjust memory buffer address wrapping - to match the uploaded bitmap width
(gdb) restore logo.bin binary 0x60038000 0 0x10000
Restoring binary file logo.bin into memory (0x60038000 to 0x60040000)
(gdb) set *((int*)0x60030004)=0x00000003
The riscv_frame_cache's start_addr is 0 (from the get_frame_func).
Forcing it to the value of the PC (0x000000002022037a) to avoid the riscv_scan_prologue reading between 0-99 addr
esses.
The riscv_frame_cache's start_addr is 0 (from the get_frame_func).
Forcing it to the value of the PC (0x000000002022037a) to avoid the riscv_scan_prologue reading between 0-99 addr
esses.
(gdb) set *((int*)0x6003000c)=0x00000080
The riscv_frame_cache's start_addr is 0 (from the get_frame_func).
Forcing it to the value of the PC (0x000000002022037a) to avoid the riscv_scan_prologue reading between 0-99 addr
esses.
(gdb)
Restoring binary file logo.bin into memory (0x60038000 to 0x60040000)
(gdb) set *((int*)0x60030004)=0x00000003
The riscv_frame_cache's start_addr is 0 (from the get_frame_func).
Forcing it to the value of the PC (0x000000002022037a) to avoid the riscv_scan_prologue reading between 0-99 addr
esses.
The riscv_frame_cache's start_addr is 0 (from the get_frame_func).
Forcing it to the value of the PC (0x000000002022037a) to avoid the riscv_scan_prologue reading between 0-99 addr
esses.
(gdb) set *((int*)0x6003000c)=0x00000080
The riscv_frame_cache's start_addr is 0 (from the get_frame_func).
Forcing it to the value of the PC (0x000000002022037a) to avoid the riscv_scan_prologue reading between 0-99 addr
esses.
(gdb)
After executing all three commands the HDMI output should present the buffer content tiled.